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MLIR n-D vector products are presently represented just like the (n-1)-D arrays of 1-D vectors whenever lowered so you can LLVM

MLIR n-D vector products are presently represented just like the (n-1)-D arrays of 1-D vectors whenever lowered so you can LLVM

MLIR n-D vector products are presently represented just like the (n-1)-D arrays of 1-D vectors whenever lowered so you can LLVM

The newest implication of the physical HW constraints towards programming model is actually this option usually do not list dynamically across the resources reports: a join document can generally not listed dynamically. For the reason that the sign in number is restricted and something either web must unroll clearly discover fixed register numbers or wade courtesy memory. It is a limitation familiar in order to CUDA programmers: when saying an exclusive float a good ; and then indexing that have an active really worth causes therefore-called regional recollections need (i.e. roundtripping to help you memory).

Implication towards codegen ¶

It introduces the results toward fixed compared to vibrant indexing talked about before: extractelement , insertelement and you may shufflevector for the n-D vectors within the MLIR only help static indicator. Dynamic indices are only supported to your very slight step 1-D vector but not the new external (n-1)-D . To other instances, explicit stream / stores are needed.

  1. Loops to vector beliefs is actually secondary dealing with of vector values, they must run-on direct load / shop surgery more than n-D vector versions.
  2. Immediately following an n-D vector types of are loaded with the an SSA well worth (which can or may well not are now living in n information, which have otherwise in the place of spilling, when ultimately reduced), it could be unrolled so you’re able to faster k-D vector models and processes one to correspond to the fresh new HW. It quantity of MLIR codegen resembles sign in allotment and you can spilling you to are present far later on throughout the LLVM tube.
  3. HW could possibly get support >1-D vectors with intrinsics for secondary handling throughout these vectors. These may getting targeted as a result of specific vector_throw surgery out-of MLIR k-D vector brands and operations to help you LLVM step 1-D vectors + intrinsics.

Rather, i argue that privately lowering in order to a great linearized abstraction hides aside the brand new codegen complexities connected with recollections accesses by giving an incorrect effect out-of magical active indexing across the registers. As an alternative we choose create people most explicit inside the MLIR and you will make it codegen to understand more about tradeoffs. Various other HW will require additional tradeoffs in the brands employed in measures step one., dos. and you will 3.

Choices generated during the MLIR level get implications on a good much later phase inside LLVM (shortly after check in allotment). We do not think to reveal questions about acting from sign in allowance and you will spilling so you’re able to MLIR clearly. Instead, for every address commonly expose a couple of “good” address functions and you can letter-D vector items, regarding the will cost you you to definitely PatterRewriters in the MLIR height could well be in a position to target. Particularly costs at MLIR peak would-be conceptual and you will utilized to have ranks, maybe not to own particular overall performance acting. Afterwards such as for example costs was discovered.

Implication on Lowering so you can Accelerators ¶

To target accelerators that support higher dimensional vectors natively, we can start from either 1-D or n-D vectors in MLIR and use vector.cast to flatten the most minor dimensions to 1-D vector where K is an appropriate constant. Then, the existing lowering to LLVM-IR immediately applies, with extensions for accelerator-specific intrinsics.

It is the role of an Accelerator-specific vector dialect (see codegen flow in the figure above) to lower the vector.cast . Accelerator -> LLVM lowering would then consist of a bunch of Accelerator -> Accelerator rewrites to perform the casts composed with Accelerator -> LLVM conversions + intrinsics that operate on 1-D vector .

Some of those rewrites may need extra handling, especially if a reduction is involved. For example, vector.cast %0: vector to vector when K != K1 * … * Kn and some arbitrary irregular vector.cast %0: vector to vector may introduce masking and intra-vector shuffling that may not be worthwhile or even feasible, i.e. infinite cost.

However vector.cast %0: vector to vector when K = K1 * … * Kn should be close to a noop.

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